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» High Level Synthesis Of Multi-Precision Data Flow Graphs
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VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
14 years 4 months ago
High Level Synthesis Of Multi-Precision Data Flow Graphs
Vikas Agrawal, Anand Pande, Mahesh Mehendale
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
13 years 8 months ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
13 years 9 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 8 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
DAC
1996
ACM
13 years 8 months ago
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
Elisabeth Berrebi, Polen Kission, Serge Vernalde, ...