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» High Level Synthesis of Timed Asynchronous Circuits
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ASAP
2002
IEEE
105views Hardware» more  ASAP 2002»
13 years 10 months ago
Implications of Programmable General Purpose Processors for Compression/Encryption Applications
With the growth of the Internet and mobile communication industry, multimedia applications form a dominant computer workload. Media workloads are typically executed on Application...
Byeong Kil Lee, Lizy Kurian John
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 9 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
CGF
2006
173views more  CGF 2006»
13 years 5 months ago
C-BDAM - Compressed Batched Dynamic Adaptive Meshes for Terrain Rendering
We describe a compressed multiresolution representation for supporting interactive rendering of very large planar and spherical terrain surfaces. The technique, called Compressed ...
Enrico Gobbetti, Fabio Marton, Paolo Cignoni, Marc...
TVLSI
2002
144views more  TVLSI 2002»
13 years 4 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail
ISCAS
2006
IEEE
169views Hardware» more  ISCAS 2006»
13 years 11 months ago
An Address-Event Image Sensor Network
We discuss an imaging architecture for sensor pixel in the ALOHA signals an event when a certain amount network applications, that employs a 32 x 32 Address-Event of photons are re...
Thiago Teixeira, Eugenio Culurciello, Andreas G. A...