249 search results - page 5 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
ICCAD
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ASYNC
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
ASYNC
2007
IEEE
14 years 4 days ago
2007
IEEE
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
ICCAD
2006
IEEE
13 years 11 months ago
2006
IEEE
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
VLSID
1999
IEEE
13 years 10 months ago
1999
IEEE
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...