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» High Performance Array Processor for Video Decoding
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CF
2007
ACM
13 years 9 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
Juan M. Cebrian, Juan L. Aragón, José...
ICCD
2006
IEEE
275views Hardware» more  ICCD 2006»
14 years 2 months ago
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
Tinoosh Mohsenin, Bevan M. Baas
JSA
2006
167views more  JSA 2006»
13 years 5 months ago
Pattern-driven prefetching for multimedia applications on embedded processors
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
CODES
2005
IEEE
13 years 10 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
VLSID
2008
IEEE
93views VLSI» more  VLSID 2008»
13 years 11 months ago
Watermarking Video Clips with Workload Information for DVS
We present a lightweight scheme for watermarking or annotating video clips with information describing the workload that would be incurred while decoding the clip. This informatio...
Yicheng Huang, Samarjit Chakraborty, Ye Wang