Sciweavers

142 search results - page 3 / 29
» High Performance Pipelined Process Migration with RDMA
Sort
View
APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
13 years 9 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 9 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
EUROSYS
2006
ACM
14 years 2 months ago
The SMART way to migrate replicated stateful services
Many stateful services use the replicated state machine approach for high availability. In this approach, a service runs on multiple machines to survive machine failures. This pap...
Jacob R. Lorch, Atul Adya, William J. Bolosky, Ron...
GECCO
2009
Springer
156views Optimization» more  GECCO 2009»
13 years 12 months ago
Characterizing the genetic programming environment for fifth (GPE5) on a high performance computing cluster
Solving complex, real-world problems with genetic programming (GP) can require extensive computing resources. However, the highly parallel nature of GP facilitates using a large n...
Kenneth Holladay
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
13 years 10 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar