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CHARME
2005
Springer
119views Hardware» more  CHARME 2005»
13 years 11 months ago
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
Petr Matousek, Ales Smrcka, Tomás Vojnar
VLSID
2005
IEEE
127views VLSI» more  VLSID 2005»
13 years 11 months ago
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pa...
APN
2003
Springer
13 years 10 months ago
Model Checking Safety Properties in Modular High-Level Nets
Model checking by exhaustive state space enumeration is one of the most developed analysis methods for distributed event systems. Its main problem—the size of the state spaces—...
Marko Mäkelä
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
13 years 9 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
IFM
2004
Springer
185views Formal Methods» more  IFM 2004»
13 years 10 months ago
Object-Oriented Modelling with High-Level Modular Petri Nets
Abstract. In this paper, we address the problem of expressing objectoriented concepts in terms of Petri nets. This is interesting, first, as a possibility of representing concurre...
Cécile Bui Thanh, Hanna Klaudel