15 search results - page 3 / 3 » High-Level Synthesis for FPGAs: From Prototyping to Deployme... |
JSA
2007
13 years 4 months ago
2007
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
FCCM
2011
IEEE
12 years 8 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based envir...
IGARSS
2010
13 years 2 months ago
2010
The Level 1 Processing of SMOS transforms the data acquired by MIRAS (Microwave Imaging Radiometer with Aperture Synthesis) into geolocated TOA Brightness Temperatures, providing ...
FPGA
2001
ACM
13 years 9 months ago
2001
ACM
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...