181 search results - page 1 / 37 » High-level area and power estimation for VLSI circuits |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...