13 search results - page 2 / 3 » High-level power estimation and the area complexity of Boole... |
FOCS
2007
IEEE
13 years 9 months ago
2007
IEEE
We develop a new technique of proving lower bounds for the randomized communication complexity of boolean functions in the multiparty `Number on the Forehead' model. Our meth...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
AHS
2007
IEEE
13 years 9 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...