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DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 9 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
13 years 11 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 2 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband
AUSAI
2006
Springer
13 years 9 months ago
Hardware Implementation of Temporal Nonmonotonic Logics
Abstract. In order to apply nonmonotonic logics for specifying industrial automation controllers, we define (1) a method to extend atemporal nonmonotonic logics with temporal opera...
Insu Song, Guido Governatori
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
13 years 9 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...