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» High-performance routing at the nanometer scale
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NETWORK
2008
153views more  NETWORK 2008»
13 years 5 months ago
IEEE 802.11s: WLAN mesh standardization and high performance extensions
In recent years, remarkable market competition and economy of scale has resulted in the price erosion of wireless devices for consumer electronics. Especially for wireless data ne...
Guido R. Hiertz, Yunpeng Zang, Sebastian Max, Thom...
DAC
2011
ACM
12 years 5 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
DATE
2005
IEEE
101views Hardware» more  DATE 2005»
13 years 11 months ago
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
Christophe Alexandre, Hugo Clément, Jean-Pa...
DAC
2011
ACM
12 years 5 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
11 years 7 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...