As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
In this paper we propose a technique to determine accurate interconnect extraction corners for a 65-nm design using parametric RC extraction and timing analysis. We calculate the ...
Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa ...
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed an...
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, L...
Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and ...
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...