183 search results - page 2 / 37 » History-based memory mode prediction for improving memory pe... |
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
CLUSTER
2004
IEEE
13 years 9 months ago
2004
IEEE
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Chip multiprocessors enable continued performance scaling with increasingly many cores per chip. As the throughput of computation outpaces available memory bandwidth, however, the...
RTAS
2010
IEEE
13 years 3 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...