46 search results - page 1 / 10 » How to Transform an Architectural Synthesis Tool for Low Pow... |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
IAJIT
2010
13 years 3 months ago
2010
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
SBCCI
2009
ACM
13 years 9 months ago
2009
ACM
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents a novel architecture using the decorrelating (DECOR) transformation technique when applied to an LMS adaptive filter. The DECOR transform has been evaluated pr...