3 search results - page 1 / 1 » IDD Waveforms Analysis for Testing of Domino and Low Voltage... |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k tra...