3 search results - page 1 / 1 » ILP Based Gate Leakage Optimization Using DKCMOS Library dur... |
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
DAC
2008
ACM
13 years 6 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...