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» IP Reuse in the System on a Chip Era
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ISSS
2000
IEEE
129views Hardware» more  ISSS 2000»
13 years 9 months ago
IP Reuse in the System on a Chip Era
Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a busin...
Warren Savage, John Chilton, Raul Camposano
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
13 years 9 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
ASPDAC
2000
ACM
99views Hardware» more  ASPDAC 2000»
13 years 9 months ago
Reuse and protection of intellectual property in the SpecC system
— In system-level design, the key to cope with the complexities involved with System-on-Chip (SOC) designs, is the reuse of Intellectual Property (IP). With the increasing demand...
Rainer Dömer, Daniel Gajski
DAC
1999
ACM
13 years 9 months ago
Panel: What is the Proper System on Chip Design Methodology
ion model or flexible PCB solutions cannot offer a valid solution for the next millinium SoCs . James G. Dougherty, Integrated Systems Silicon LTD, Belfast, Northern Ireland ISS an...
Richard Goering, Pierre Bricaud, James G. Doughert...
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
14 years 5 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf