27 search results - page 1 / 6 » IP Validation for FPGAs Using Hardware Object Technology |
FPL
1999
Springer
13 years 9 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
ASPDAC
2004
ACM
13 years 8 months ago
2004
ACM
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
CAI
2004
Springer
13 years 4 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
DELTA
2006
IEEE
13 years 8 months ago
2006
IEEE
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resourc...
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse o...