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» IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Ap...
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IPPS
2006
IEEE
13 years 11 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov
ERSA
2010
217views Hardware» more  ERSA 2010»
13 years 3 months ago
FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images
The pixel purity index algorithm is employed in remote sensing for analyzing hyperspectral images. A single pixel usually covers several different materials, and its observed spect...
Carlos González, Daniel Mozos, Javier Resan...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
13 years 11 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
13 years 10 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...