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» Imaging with THZ Pulses
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ISCAS
2006
IEEE
169views Hardware» more  ISCAS 2006»
14 years 2 days ago
An Address-Event Image Sensor Network
We discuss an imaging architecture for sensor pixel in the ALOHA signals an event when a certain amount network applications, that employs a 32 x 32 Address-Event of photons are re...
Thiago Teixeira, Eugenio Culurciello, Andreas G. A...
JRTIP
2008
118views more  JRTIP 2008»
13 years 6 months ago
Custom parallel caching schemes for hardware-accelerated image compression
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...
FPGA
2009
ACM
200views FPGA» more  FPGA 2009»
14 years 26 days ago
FPGA-based front-end electronics for positron emission tomography
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
MR
2010
120views Robotics» more  MR 2010»
13 years 4 months ago
Automated inspection and classification of flip-chip-contacts using scanning acoustic microscopy
Industrial applications often require failure analysis methods working non-destructively, enabling either a rapid quality control or fault isolation and defect localization prior ...
S. Brand, P. Czurratis, P. Hoffrogge, M. Petzold
ICIP
2008
IEEE
14 years 15 days ago
Buffer constrained rate control for low bitrate dual-frame video coding
In dual-frame video coding, one long-term reference (LTR) and one short-term reference (STR) frames are used for motion estimation and compensation. In previous work, it was shown...
Mayank Tiwari, Theodore Groves, Pamela C. Cosman