104 search results - page 1 / 21 » Impact Analysis of Process Variability on Clock Skew |
ISQED
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
DAC
2009
ACM
13 years 11 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on m...