Sciweavers

76 search results - page 15 / 16
» Impact of NBTI on FPGAs
Sort
View
JRTIP
2008
118views more  JRTIP 2008»
13 years 5 months ago
Custom parallel caching schemes for hardware-accelerated image compression
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...
DAC
2005
ACM
14 years 6 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
14 years 2 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
DATE
1998
IEEE
114views Hardware» more  DATE 1998»
13 years 10 months ago
Design Of Future Systems
Near-future linac projects put yet unreached requirements on the LLRF control hardware in both performance and manageability. Meeting their field stability targets requires a clea...
Ian Page
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
13 years 9 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose