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» Impact of Self-Heating in Wire Interconnection on Timing
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FPL
2005
Springer
112views Hardware» more  FPL 2005»
13 years 10 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
INTEGRATION
2008
96views more  INTEGRATION 2008»
13 years 4 months ago
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
13 years 11 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
GLVLSI
2006
IEEE
144views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Crosstalk analysis in nanometer technologies
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
Shahin Nazarian, Ali Iranli, Massoud Pedram
DAC
2002
ACM
14 years 5 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge