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GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
13 years 10 months ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
14 years 1 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
13 years 11 months ago
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
13 years 11 months ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
13 years 11 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...