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» Implementation of Near Shannon Limit Error-Correcting Codes ...
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FCCM
2000
IEEE
71views VLSI» more  FCCM 2000»
13 years 9 months ago
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
Benjamin A. Levine, R. Reed Taylor, Herman Schmit
SIPS
2008
IEEE
13 years 11 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
FCCM
2004
IEEE
103views VLSI» more  FCCM 2004»
13 years 9 months ago
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
Jian Liang, Russell Tessier, Dennis Goeckel
MSO
2003
13 years 6 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan