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ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
10 years 4 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
NIPS
2007
10 years 1 months ago
A neural network implementing optimal state estimation based on dynamic spike train decoding
It is becoming increasingly evident that organisms acting in uncertain dynamical environments often employ exact or approximate Bayesian statistical calculations in order to conti...
Omer Bobrowski, Ron Meir, Shy Shoham, Yonina C. El...
CORR
2008
Springer
105views Education» more  CORR 2008»
9 years 12 months ago
On Full Diversity Space-Time Block Codes with Partial Interference Cancellation Group Decoding
In this paper, we propose a partial interference cancellation (PIC) group decoding strategy/scheme for linear dispersive space-time block codes (STBC) and a design criterion for th...
Xiaoyong Guo, Xiang-Gen Xia
ASPDAC
2006
ACM
123views Hardware» more  ASPDAC 2006»
10 years 5 months ago
Implementation of H.264/AVC decoder for mobile video applications
- This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a ded...
Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea ...
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
10 years 5 months ago
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder
In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consum...
Matjaz Verderber, Andrej Zemva, Damjan Lampret
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