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» Implementing a Register in a Dynamic Distributed System
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ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
13 years 10 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
HPCA
2012
IEEE
12 years 14 days ago
Flexible register management using reference counting
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
Steven Battle, Andrew D. Hilton, Mark Hempstead, A...
IPPS
2007
IEEE
13 years 11 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...
PLDI
1998
ACM
13 years 9 months ago
Quality and Speed in Linear-scan Register Allocation
A linear-scan algorithm directs the global allocation of register candidates to registers based on a simple linear sweep over the program being compiled. This approach to register...
Omri Traub, Glenn H. Holloway, Michael D. Smith
PPL
2006
81views more  PPL 2006»
13 years 4 months ago
Microthreading a Model for Distributed Instruction-level Concurrency
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
Chris R. Jesshope