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» Implication graph based domino logic synthesis
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ITC
2003
IEEE
148views Hardware» more  ITC 2003»
13 years 10 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
DMDW
2000
173views Management» more  DMDW 2000»
13 years 6 months ago
A quality-based framework for physical data warehouse design
Data warehousing is a software infrastructure which supports OLAP applications by providing a collection of tools which allow data extraction and cleaning, data integration and ag...
Mokrane Bouzeghoub, Zoubida Kedad
TCAD
2002
121views more  TCAD 2002»
13 years 4 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
FCCM
1997
IEEE
199views VLSI» more  FCCM 1997»
13 years 9 months ago
The RAW benchmark suite: computation structures for general purpose computing
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut o...
Jonathan Babb, Matthew Frank, Victor Lee, Elliot W...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 1 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson