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» Improve Chip Pin Performance Using Optical Interconnects
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SLIP
2004
ACM
13 years 9 months ago
Optical solutions for system-level interconnect
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Ian O'Connor
MICRO
2006
IEEE
104views Hardware» more  MICRO 2006»
13 years 10 months ago
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the develo...
Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jo...
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
14 years 1 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
ASPDAC
1999
ACM
137views Hardware» more  ASPDAC 1999»
13 years 8 months ago
A Performance-Driven I/O Pin Routing Algorithm
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arun...
HOTI
2008
IEEE
13 years 10 months ago
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-onchip...
Michele Petracca, Benjamin G. Lee, Keren Bergman, ...