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ICCAD
1999
IEEE
79views Hardware» more  ICCAD 1999»
13 years 9 months ago
Improved interconnect sharing by identity operation insertion
This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analys...
Dirk Herrmann, Rolf Ernst
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...
OSDI
2000
ACM
13 years 6 months ago
Taming the Memory Hogs: Using Compiler-Inserted Releases to Manage Physical Memory Intelligently
Out-of-core applications consume physical resources at a rapid rate, causing interactive applications sharing the same machine to exhibit poor response times. This behavior is the...
Angela Demke Brown, Todd C. Mowry
DAC
2003
ACM
14 years 5 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
13 years 11 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...