37 search results - page 7 / 8 » Improving Execution Speed of FPGA using Dynamically Reconfig... |
IPPS
2009
IEEE
14 years 12 days ago
2009
IEEE
In this paper we investigate feedback-directed dynamic selection between different implementations of atomic blocks. We initially execute atomic blocks using STM with optimistic c...
ICPP
2003
IEEE
13 years 11 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
PACS
2000
Springer
13 years 9 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
MJ
2011
13 years 21 days ago
2011
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...