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FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 7 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
ARC
2010
Springer
387views Hardware» more  ARC 2010»
14 years 17 days ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides
ICCS
2005
Springer
13 years 11 months ago
Vectorized Sparse Matrix Multiply for Compressed Row Storage Format
Abstract. The innovation of this work is a simple vectorizable algorithm for performing sparse matrix vector multiply in compressed sparse row (CSR) storage format. Unlike the vect...
Eduardo F. D'Azevedo, Mark R. Fahey, Richard Tran ...
SAMOS
2010
Springer
13 years 4 months ago
A Polymorphic Register File for matrix operations
—Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes and shapes. We propose a register file organization whic...
Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Ga...
IPPS
2007
IEEE
14 years 1 days ago
Memory Optimizations For Fast Power-Aware Sparse Computations
— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
Konrad Malkowski, Padma Raghavan, Mary Jane Irwin