14 search results - page 2 / 3 » Improving SMT performance: an application of genetic algorit... |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
ISCA
2010
IEEE
13 years 3 months ago
2010
IEEE
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
ISCA
1994
IEEE
13 years 9 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
IEEEPACT
1999
IEEE
13 years 9 months ago
1999
IEEE
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...