71 search results - page 2 / 15 » Improving memory bank-level parallelism in the presence of p... |
ICPP
2003
IEEE
13 years 10 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
ISPDC
2010
IEEE
13 years 3 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
ICS
2000
Tsinghua U.
13 years 9 months ago
2000
Tsinghua U.
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...