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ICASSP
2008
IEEE
13 years 11 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
DATE
2002
IEEE
161views Hardware» more  DATE 2002»
13 years 9 months ago
Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
Heiko Michel, Alexander Worm, Norbert Wehn, Michae...
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 9 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
FPL
2004
Springer
128views Hardware» more  FPL 2004»
13 years 10 months ago
Design and Implementation of a CFAR Processor for Target Detection
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
Cesar Torres-Huitzil, René Cumplido-Parra, ...