38 search results - page 7 / 8 » Increasing memory miss tolerance for SIMD cores |
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...
SIGMETRICS
1993
ACM
13 years 9 months ago
1993
ACM
Recently there has been a surge of interest in developing performance debugging tools to help programmers tune their applications for better memory performance [2, 4, 10]. These t...
SIGARCH
2008
13 years 5 months ago
2008
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
ISCA
2003
IEEE
13 years 11 months ago
2003
IEEE
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
DSN
2005
IEEE
13 years 11 months ago
2005
IEEE
Device scaling and large scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing par...