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CODES
2006
IEEE
13 years 12 months ago
Increasing the throughput of an adaptive router in network-on-chip (NoC)
In this paper, we propose a simple and efficient mechanism to increase the throughput of an adaptive router in Networkon-Chip (NoC). One of the most serious disadvantages of fully...
Seung Eun Lee, Nader Bagherzadeh
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 7 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 3 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
13 years 11 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
CODES
2007
IEEE
14 years 4 days ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha