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» Incremental SAT Instance Generation for SAT-based ATPG
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DDECS
2009
IEEE
128views Hardware» more  DDECS 2009»
14 years 10 days ago
A fast untestability proof for SAT-based ATPG
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
Daniel Tille, Rolf Drechsler
ETS
2010
IEEE
150views Hardware» more  ETS 2010»
13 years 6 months ago
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
Daniel Tille, Stephan Eggersglüß, Rene ...
SAT
2007
Springer
184views Hardware» more  SAT 2007»
13 years 11 months ago
Circuit Based Encoding of CNF Formula
In this paper a new circuit sat based encoding of boolean formula is proposed. It makes an original use of the concept of restrictive models introduced by Boufkhad to polynomially ...
Gilles Audemard, Lakhdar Sais
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 2 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
DSD
2010
IEEE
171views Hardware» more  DSD 2010»
13 years 4 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt