15 search results - page 3 / 3 » Incremental SAT Instance Generation for SAT-based ATPG |
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
VLSID
2010
IEEE
13 years 3 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
TCAD
2008
13 years 5 months ago
2008
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
ICCAD
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper addresses SAT-based Unbounded Model Checking based on Craig Interpolants. This recently introduced methodology is often able to outperform BDDs and other SAT-based tech...
CAV
2004
Springer
13 years 9 months ago
2004
Springer
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...