27 search results - page 2 / 6 » Inductance Aware Interconnect Scaling |
TVLSI
2002
13 years 4 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
In the multi-GHz frequency domain, inductive and capacitive parasitics of interconnects can cause significant 'ringing' or overdamping, which may lead to false switching...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...