13 search results - page 1 / 3 » Inductive Noise Reduction at the Architectural Level |
VLSID
2000
IEEE
13 years 9 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
TVLSI
2002
13 years 4 months ago
2002
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...