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Inductive Noise Reduction at the Architectural Level

12 years 1 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Deactivating idle units provides needed reductions in power consumption. However, it introduces inductive noise that can limit voltage scaling. The paper introduces an architectural approach for reducing this inductive noise by providing gradual activation and deactivation of functional blocks. This technique provides a 2x reduction in ground bounce current on a 16 bit ALU simulated in SPICE, while reducing simulated SPEC95 performance by less than 5% on a typical superscalar architecture. It has also been demonstrated to be effective for image processing SIMD architectures.
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv
Added 01 Aug 2010
Updated 01 Aug 2010
Type Conference
Year 2000
Where VLSID
Authors Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
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