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» Inductive Noise Reduction at the Architectural Level
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DATE
2003
IEEE
130views Hardware» more  DATE 2003»
13 years 10 months ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
PACS
2000
Springer
118views Hardware» more  PACS 2000»
13 years 8 months ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
HPCA
2006
IEEE
13 years 10 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
ASAP
2008
IEEE
117views Hardware» more  ASAP 2008»
13 years 6 months ago
Reconfigurable acceleration of microphone array algorithms for speech enhancement
Microphone arrays play an important role in noise reduction and speech enhancement. Their algorithms are based on beamforming, which reduces the level of localized and ambient noi...
Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao...
TVLSI
2010
12 years 11 months ago
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
Hamed F. Dadgour, Kaustav Banerjee