42 search results - page 3 / 9 » Inductive interconnect width optimization for low power |
TVLSI
2010
12 years 12 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
Abstract— The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of...