Sciweavers

24 search results - page 4 / 5
» Influence of Leakage Reduction Techniques on Delay Leakage U...
Sort
View
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 6 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
13 years 12 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
ISQED
2005
IEEE
87views Hardware» more  ISQED 2005»
13 years 11 months ago
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...
Puneet Gupta, Andrew B. Kahng, Puneet Sharma
PATMOS
2007
Springer
14 years 3 days ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
TCAD
2008
172views more  TCAD 2008»
13 years 5 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...