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GECCO
2003
Springer
129views Optimization» more  GECCO 2003»
13 years 10 months ago
Inherent Fault Tolerance in Evolved Sorting Networks
This poster paper summarizes our research on fault tolerance arising as a by-product of the evolutionary computation process. Past research has shown evidence of robustness emergin...
Rob Shepherd, James A. Foster
DSN
2007
IEEE
13 years 11 months ago
Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance
A new approach is proposed that exploits repetition inherent in programs to provide low-overhead transient fault protection in a processor. Programs repeatedly execute the same in...
Vimal K. Reddy, Eric Rotenberg
AHS
2007
IEEE
262views Hardware» more  AHS 2007»
13 years 11 months ago
Addressing the Metric Challenge: Evolved versus Traditional Fault Tolerant Circuits
The field of Evolvable Hardware, applying artificial evolution to the design of digital and analogue hardware is around ten years old. However, the field is far from reaching m...
Pauline C. Haddow, Morten Hartmann, Asbjørn...
PPSN
2004
Springer
13 years 10 months ago
Evolving Genetic Regulatory Networks for Hardware Fault Tolerance
We present a new approach that is able to produce an increased fault tolerance in bio-inspired electronic circuits. To this end, we designed hardwarefriendly genetic regulatory net...
Arne Koopman, Daniel Roggen
TCAD
2010
105views more  TCAD 2010»
12 years 11 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki