This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
This paper describes our methodology for building conformant planners, which is based on recent advances in the theory of action and change and answer set programming. The develop...
Phan Huy Tu, Tran Cao Son, Michael Gelfond, A. Ric...