It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...