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CODES
2007
IEEE
14 years 3 days ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
CODES
2008
IEEE
14 years 7 days ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
EDCC
2006
Springer
13 years 9 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
CODES
2004
IEEE
13 years 9 months ago
Dynamic overlay of scratchpad memory for energy minimization
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
Manish Verma, Lars Wehmeyer, Peter Marwedel
ISLPED
1997
ACM
108views Hardware» more  ISLPED 1997»
13 years 10 months ago
Techniques for low energy software
The energy consumption of a system depends upon the hardware and software component of a system. Since it is the software which drives the hardware in most systems, decisions take...
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwi...