15 search results - page 2 / 3 » Instruction Wake-Up in Wide Issue Superscalars |
ISCA
2002
IEEE
13 years 11 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
ISCA
2000
IEEE
13 years 10 months ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
ISCA
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
IEEEPACT
1999
IEEE
13 years 10 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...